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? semiconductor components industries, llc, 2012 november, 2012 ? rev. 2 1 publication order number: ncp6354/d ncp6354 3mhz, 2a fixed-frequency synchronous buck converter high efficiency, low ripple, adjustable output voltage the ncp6354, a synchronous buck converter, which is optimized to supply the different sub systems of portable applications powered by one cell li ? ion or three cell alkaline/nicd/nimh batteries. the device is able to deliver up to 2 a on an external adjustable voltage. operation with 3 mhz switching frequency allows employing small size inductor and capacitors. input supply voltage feedforward control is employed to deal with wide input voltage range. synchronous rectification offers improved system efficiency. the ncp6354 is in a space saving, low profile 2.0x2.0x0.75 mm wdfn ? 8 package. features ? 2.3 v to 5.5 v input voltage range ? external adjustable voltage ? up to 2 a output current ? 3 mhz switching frequency ? synchronous rectification ? enable input ? power good output ? soft start ? over current protection ? active discharge when disabled ? thermal shutdown protection ? wdfn ? 8, 2x2 mm, 0.5 mm pitch package ? maximum 0.8 mm height for super thin applications ? these are pb ? free devices typical applications ? cellular phones, smart phones, and pdas ? portable media players ? digital still cameras ? wireless and dsl modems ? usb powered devices ? point of load ? game and entertainment system marking diagram http://onsemi.com wdfn8 case 511be block diagram 1 a2 = specific device code m = date code = pb ? free package a2m 1 (*note: microdot may be in either location) 1 2 3 4 5 8 7 6 9 pgnd sw agnd fb pvin avin pg en (top view) see detailed ordering, marking and shipping information in the package dimensions section on page 14 of this data sheet. ordering information
ncp6354 http://onsemi.com 2 1uh vo = 0.6v to vin cout 10uf pgnd fb pvin en sw agnd avin pg cin 10uf rpg 1m vin = 2.3v to 5.5v power good enable r1 r2 cfb ncp6354 figure 1. typical application circuit pin description pin name type description 1 pgnd power ground power ground for power, analog blocks. must be connected to the system ground. 2 sw power output switch power pin connects power transistors to one end of the inductor. 3 agnd analog ground analog ground analog and digital blocks. must be connected to the system ground. 4 fb analog input feedback voltage from the buck converter output. this is the input to the error amplifier. this pin is connected to the resistor divider network between the output and agnd. 5 en digital input enable of the ic. high level at this pin enables the device. low level at this pin disables the device. 6 pg digital output pg pin is for ncp6354 with power good option. it is open drain output. low level at this pin indicates the device is not in power good, while high impedance at this pin indicates the device is in power good. 7 avin analog input analog supply. this pin is the analog and the digital supply of the device. an optional 1 f or larger ceramic capacitor bypasses this input to the ground. this capacitor should be placed as close as possible to this input. 8 pvin power input power supply input. this pin is the power supply of the device. a 10 f or larger ceramic capacitor must bypass this input to the ground. this capacitor should be placed as close a possible to this input. 9 pad exposed pad exposed pad. must be soldered to system ground to achieve power dissipation performances. this pin is internally unconnected
ncp6354 http://onsemi.com 3 pwm / pfm control reference voltage l cout 1uh 10uf logic control & current limit & thermal shutdown cin 10uf rpg 1m uvlo vin vo power good enable pvin 8 sw 2 pgnd 1 en 5 pg 6 fb 4 avin 7 agnd 3 r1 r2 cfb error amp figure 2. functional block diagram. maximum ratings rating symbol value unit min max input supply voltage to gnd v pvin , v avin ? 0.3 7.0 v switch node to gnd v sw ? 0.3 7.0 v en, pg to gnd v en , v pg ? 0.3 7.0 v fb to gnd v fb ? 0.3 2.5 v human body model (hbm) esd rating are (note 1) esd hbm 2000 v machine model (mm) esd rating (note 1) esd mm 200 v latchup current (note 2) i lu ? 100 100 ma operating junction temperature range (note 3) t j ? 40 125 c operating ambient temperature range t a ? 40 85 c storage temperature range t stg ? 55 150 c thermal resistance junction ? to ? top case (note 4) r jc 12 c/w thermal resistance junction ? to ? board (note 4) r jb 30 c/w thermal resistance junction ? to ? ambient (note 4) r ja 62 c/w power dissipation (note 5) p d 1.6 w moisture sensitivity level (note 6) msl 1 ? stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and passes the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22 ? a114. machine model (mm) 200 v per jedec standard: jesd22 ? a115. 2. latchup current per jedec standard: jesd78 class ii. 3. the thermal shutdown set to 150 c (typical) avoids potential irreversible damage on the device due to power dissipation. 4. the thermal resistance values are dependent of the pcb heat dissipation. board used to drive these data was an 80 x 50mm ncp6 334evb board. it is a multilayer board with 1 ? once internal power and ground planes and 2 ? once copper traces on top and bottom of the board. if the copper trances of top and bottom are 1 ? once too, r jc = 11 c/w, r jb = 30 c/w, and r ja = 72 c/w. 5. the maximum power dissipation (pd) is dependent on input voltage, maximum output current and external components selected. 6. moisture sensitivity level (msl): 1 per ipc/jedec standard: j ? std ? 020a.
ncp6354 http://onsemi.com 4 electrical characteristics (v in = 3.6 v, v out = 1.8 v, l = 1 h, c = 10 f, typical values are referenced to t j = 25 c, min and max values are referenced to t j up to 125 c. unless other noted.) characteristics test conditions symbol min typ max unit supply voltage input voltage v in range (note 9) v in 2.3 ? 5.5 v supply current v in quiescent supply current en high, no load i q ? 5 ? ma v in shutdown current en low i sd ? ? 1 a output voltage output voltage range (note 7) v out 0.6 ? vin v fb voltage v fb 594 600 606 mv fb voltage in load regulation v in = 3.6 v, i out from 200 ma to i outmax , (note 7) ? ? 0.5 ? %/a fb voltage in line regulation i out = 200 ma, v in from max(v nom + 0.5 v, 2.3 v) to 5.5 v (note 7) ? 0 ? %/v maximum duty cycle (note 7) d max ? 100 ? % output current output current capability (note 7) i outmax 2.0 ? ? a output peak current limit i lim 2.3 2.8 3.3 a voltage monitor v in uvlo falling threshold v inuv ? ? ? 2.3 v v in uvlo hysteresis v inhys 60 ? 2 0 0 mv power good low threshold v out falls down to cross the threshold (percentage of fb voltage) v pgl 87 90 92 % power good hysteresis v out rises up to cross the threshold (percentage of power good low threshold (v pgl ) voltage) v pghys 0 3 5 % power good high delay in start up from en rising edge to pg going high. td pgh1 ? 1.15 ? ms power good low delay in shut down from en falling edge to pg going low. (note 7) td pgl1 ? 8 ? s power good high delay in regulation from v fb going higher than 95% nominal level to pg going high. not for the first time in start up. (note 7) td pgh ? 5 ? s power good low delay in regulation from v fb going lower than 90% nominal level to pg going low. (note 7) td pgl ? 8 ? s power good pin low voltage voltage at pg pin with 5ma sink current vpg_l ? ? 0.3 v power good pin leakage current 3.6 v at pg pin when power good valid pg_lk ? ? 100 na integrated mosfets high ? side mosfet on resistance v in = 3.6 v (note 8) v in = 5 v (note 8) r on_h ? 140 130 200 ? m low ? side mosfet on resistance v in = 3.6 v (note 8) v in = 5 v (note 8) r on_l ? 110 100 140 ? m switching frequency operation frequency fsw 2.7 3.0 3.3 mhz 7. guaranteed by design, not tested in production. 8. maximum value applies for t j = 85 c. 9. operation above 5.5 v input voltage for extended periods may affect device reliability.
ncp6354 http://onsemi.com 5 electrical characteristics (v in = 3.6 v, v out = 1.8 v, l = 1 h, c = 10 f, typical values are referenced to t j = 25 c, min and max values are referenced to t j up to 125 c. unless other noted.) characteristics unit max typ min symbol test conditions soft start soft ? start time time from en to 90% of output voltage target tss ? 0.4 1 ms control logic en input high voltage ven_h 1.1 ? ? v en input low voltage ven_l ? ? 0.4 v en input hysteresis ven_hys ? 270 ? mv enable input bias current ien_bias 0.1 1 a output active discharge internal output discharge resistance from sw to pgnd r_dis 75 500 700 thermal shutdown thermal shutdown threshold tsd ? 150 ? c thermal shutdown hysteresis tsd_hys ? 25 ? c
ncp6354 http://onsemi.com 6 typical operating characterestics figure 3. standby current vs. input voltage (en = low, t a = 25 c) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2.5 3 3.5 4 4.5 5 5.5 v in , input voltage (v) i sd , v in shutdown current ( a) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ? 50 ? 25 0 25 50 75 100 125 150 t a , ambient temperature ( c) i sd , v in shutdown current ( a) figure 4. standby current vs. temperature (en = low, v in = 3.6 v) 0 2 4 6 8 10 2.5 3 3.5 4 4.5 5 5.5 figure 5. quiescent current vs. input voltage (en = high, open loop, v out = 1.8v, t a = 25 c) v in , input voltage (v) i q , v in quiescent current (ma) 0 2 4 6 8 10 ? 50 ? 25 0 25 50 75 100 125 150 t a , ambient temperature ( c) i q , v in quiescent current (ma) figure 6. quiescent current vs. temperature (en = high, open loop, v out = 1.8 v, v in = 3.6 v) figure 7. efficiency vs. output current and input voltage (v out = 1.05 v, t a = 25 c) 0 10 20 30 40 50 60 70 80 90 100 0 500 1000 1500 2000 i out , output current (ma) efficiency (%) figure 8. efficiency vs. output current and input voltage (v out = 1.8 v, t a = 25 c) v in = 2.7 v v in = 3.6 v v in = 5.5 v 0 10 20 30 40 50 60 70 80 90 100 0 500 1000 1500 2000 efficiency (%) i out , output current (ma) v in = 2.7 v v in = 3.6 v v in = 5.5 v
ncp6354 http://onsemi.com 7 typical operating characterestics 0 10 20 30 40 50 60 70 80 90 100 0 500 1000 1500 2000 figure 9. efficiency vs. output current and input voltage (v out = 3.3 v, t a = 25 c) i out , output current (ma) efficiency (%) v in = 3.6 v v in = 5.5 v 0 10 20 30 40 50 60 70 80 90 100 0 500 1000 1500 2000 i out , output current (ma) efficiency (%) figure 10. efficiency vs. output current and input voltage (v out = 4 v, t a = 25 c) v in = 4.5 v v in = 5.5 v 1.78 1.79 1.8 1.81 1.82 0 200 400 600 800 1000 1200 1400 1600 1800 2000 i out , output current (ma) v out , output voltage (v) v in = 3.6 v v in = 5.5 v v in = 2.7 v figure 11. load regulation vs. output current and input voltage (v out = 1.8 v, t a = 25 c) 1.78 1.79 1.8 1.81 1.82 0 200 400 600 800 1000 1200 1400 1600 1800 2000 t a = ? 40 c t a = 25 c t a = 85 c i out , output current (ma) v out , output voltage (v) figure 12. load regulation vs. output current and temperature (v in = 3.6 v, v out = 1.8 v) figure 13. output ripple voltage (v in = 3.6 v, v out = 1.8 v, i out = 1 a, l=1.0 h, c out = 10 f) figure 14. load transient response (v in = 3.6 v, v out = 1.8 v, i out = 500 ma to 1500 ma, l = 1.0 h, c out = 10 f) v out 5 mv/div 3 mv sw 2 v/div time: 200 ns/div ? 70 mv v out 100 mv/div 100 mv 500 ma 1500 ma i out 1 a/div sw 2 v/div time: 20 s/div
ncp6354 http://onsemi.com 8 typical operating characterestics figure 15. power up sequence and inrush current in input (v in = 3.6 v, v out = 1.8 v, i out = 0 a, l = 1.0 h, c out = 10 f) figure 16. power up sequence and power good (v in = 3.6 v, v out = 1.8 v, i out = 0 a, l = 1.0 h, c out = 10 f) figure 17. power down sequence and active output discharge (v in = 3.6 v, v out = 1.8 v, i out = 0 a, l = 1.0 h, c out = 10 f) en 5 v/div time: 100 s/div 80 ma i in 100 ma/div v out 1.0 v/div sw 5 v/div en 5 v/div v out 1.0 v/div time: 200 s/div sw 2 v/div en 5 v/div v out 1.0 v/div pg 5 v/div sw 2 v/div time: 1 ms/div pg 5 v/div
ncp6354 http://onsemi.com 9 detailed description general the ncp6354, a synchronous buck converter, which is optimized to supply the different sub systems of portable applications powered by one cell li ? ion or three cell alkaline/nicd/nimh batteries. the device is able to deliver up to 2 a on an external adjustable voltage. operation with 3 mhz switching frequency allows employing small size inductor and capacitors. input supply voltage feedforward control is employed to deal with wide input voltage range. synchronous rectification offers improved system efficiency. pwm operation the inductor current is continuous and the device operates in fixed switching frequency, which has a typical value of 3 mhz. the output voltage is regulated by on ? time pulse width modulation of the internal p ? mosfet. the internal n ? mosfet operates as synchronous rectifier and its turn ? on signal is complimentary to that of the p ? mosfet. undervoltage lockout the input voltage v in must reach or exceed 2.4 v (typical) before the ncp6354 enables the converter output to begin the start up sequence. the uvlo threshold hysteresis is typically 100 mv. enable the ncp6354 has an enable logic input pin en. a high level (above 1.1 v) on this pin enables the device to active mode. a low level (below 0.4 v) on this pin disables the device and makes the device in shutdown mode. there is an internal filter with 5 s time constant. the en pin is pulled down by an internal 10 na sink current source. in most of applications, the en signal can be programmed independently to vin power sequence. power good output for ncp6354 with power good output, the device monitors the output voltage and provides a power good output signal at the pg pin. this pin is an open ? drain output pin. to indicate the output of the converter is established, a power good signal is available. the power good signal is low when en is high but the output voltage has not been established. once the output voltage of the converter drops out below 90% of its regulation during operation, the power good signal is pulled low and indicates a power failure. a 5% hysteresis is required on power good comparator before signal going high again. soft start a soft start limits inrush current when the converter is enabled. after a minimum 300 s delay time following the enable signal, the output voltage starts to ramp up in 100 s (for external adjustable voltage devices) or with a typical 10 v/ms slew rate (for fixed voltage devices). active output discharge an output discharge operation is active in when en is low. a discharge resistor (500 typical) is enabled in this condition to discharge the output capacitor through sw pin. en pg vout 95% 90% 1.1v 0.4v 300us 1.15ms 8us 5us 8us active discharge 8us 100us figure 18. power good and active discharge timing diagram cycle ? by ? cycle current limitation the ncp6354 protects the device from over current with a fixed cycle ? by ? cycle current limitation. the typical peak current limit ilmt is 2.8 a. if inductor current exceeds the current limit threshold, the p ? mosfet will be turned off cycle ? by ? cycle. the maximum output current can be calculated by
ncp6354 http://onsemi.com 10 i max i lmt v out v in v out 2 v in f sw l (eq. 1) where v in is input supply voltage, v out is output voltage, l is inductance of the filter inductor, and f sw is 3 mhz normal switching frequency. thermal shutdown the ncp6354 has a thermal shutdown protection to protect the device from overheating when the die temperature exceeds 150 c. once the thermal protection is triggered, the fault state can be ended by re ? applying vin and/or en when the temperature drops down below 125 c. application information output filter design considerations the output filter introduces a double pole in the system at a frequency of f lc 1 2 l c (eq. 2) the internal compensation network design of the ncp6354 is optimized for the typical output filter comprised of a 1.0 h inductor and a 10 f ceramic output capacitor, which has a double pole frequency at about 50 khz. other possible output filter combinations may have a double pole around 50 khz to have optimum operation with the typical feedback network. normal selection range of the inductor is from 0.47 h to 4.7 h, and normal selection range of the output capacitor is from 4.7 f to 22 f. inductor selection the inductance of the inductor is determined by given peak ? to ? peak ripple current i l_pp of approximately 20% to 50% of the maximum output current i out_max for a trade ? off between transient response and output ripple. the inductance corresponding to the given current ripple is l v in v out v out v in f sw i l_pp (eq. 3) the selected inductor must have high enough saturation current rating to be higher than the maximum peak current that is i l_max i out_max i l_pp 2 (eq. 4) the inductor also needs to have high enough current rating based on temperature rise concern. low dcr is good for efficiency improvement and temperature rise reduction. table 1 shows some recommended inductors for high power applications and table 2 shows some recommended inductors for low power applications. table 1. list of recommended inductors for high power applications manufacturer part number case size (mm) l ( h) rated current (ma) (inductance drop) structure murata lqh44pn2r2mp0 4.0 x 4.0 x 1.8 2.2 2500 ( ? 30%) wire wound murata lqh44pn1r0np0 4.0 x 4.0 x 1.8 1.0 2950 ( ? 30%) wire wound murata lqh32pnr47nnp0 3.0 x 2.5 x 1.7 0.47 3400 ( ? 30%) wire wound table 2. list of recommended inductors for low power applications manufacturer part number case size (mm) l ( h) rated current (ma) (inductance drop) structure murata lqh44pn2r2mj0 4.0 x 4.0 x 1.1 2.2 1320 ( ? 30%) wire wound murata lqh44pn1r0nj0 4.0 x 4.0 x 1.1 1.0 2000 ( ? 30%) wire wound tdk vls201612et ? 2r2 2.0 x 1.6 x 1.2 2.2 1150 ( ? 30%) wire wound tdk vls201612et ? 1r0 2.0 x 1.6 x 1.2 1.0 1650 ( ? 30%) wire wound output capacitor selection the output capacitor selection is determined by output voltage ripple and load transient response requirement. for a given peak ? to ? peak ripple current i l_pp in the inductor of the output filter, the output voltage ripple across the output capacitor is the sum of three components as below. v out_pp v out_pp(c) v out_pp(esr) v out_pp(esl) (eq. 5) where v out_pp(c) is a ripple component by an equivalent total capacitance of the output capacitors, v out_pp(esr) is a ripple component by an equivalent esr of the output capacitors, and v out_pp(esl) is a ripple component by an equivalent esl of the output capacitors. in pwm operation mode, the three ripple components can be obtained by
ncp6354 http://onsemi.com 11 v out_pp(c) i l_pp 8 c f sw (eq. 6) v out_pp(esr) i l_pp esr (eq. 7) v out_pp(esl) esl esl l v in (eq. 8) and the peak ? to ? peak ripple current is i l_pp v in v out v out v in f sw l (eq. 9) in applications with all ceramic output capacitors, the main ripple component of the output ripple is v out_pp(c) . so that the minimum output capacitance can be calculated regarding to a given output ripple requirement v out_pp in pwm operation mode. c min i l_pp 8 v out_pp f sw (eq. 10) input capacitor selection one of the input capacitor selection guides is the input voltage ripple requirement. to minimize the input voltage ripple and get better decoupling in the input power supply rail, ceramic capacitor is recommended due to low esr and esl. the minimum input capacitance regarding to the input ripple voltage v in_pp is c in_min i out_max d d 2 v in_pp f sw (eq. 11) where d v out v in (eq. 12) in addition, the input capacitor needs to be able to absorb the input current, which has a rms value of i in_rms i out_max d d 2 (eq. 13) the input capacitor also needs to be sufficient to protect the device from over voltage spike, and normally at least a 4.7 f capacitor is required. the input capacitor should be located as close as possible to the ic on pcb. table 3. list of recommended input capacitors and output capacitors manufacturer part number case size height max (mm) c ( f) rated voltage (v) structure murata grm21br60j226me39, x5r 0805 1.4 22 6.3 mlcc tdk c2012x5r0j226m, x5r 0805 1.25 22 6.3 mlcc murata grm21br61a106ke19, x5r 0805 1.35 10 10 mlcc tdk c2012x5r1a106m, x5r 0805 1.25 10 10 mlcc murata grm188r60j106me47, x5r 0603 0.9 10 6.3 mlcc tdk c1608x5r0j106m, x5r 0603 0.8 10 6.3 mlcc murata grm188r60j475ke19, x5r 0603 0.87 4.7 6.3 mlcc design of feedback network for ncp6354 devices with an external adjustable output voltage, the output voltage is programmed by an external resistor divider connected from v out to fb and then to agnd, as shown in the typical application schematic figure 1a. the programmed output voltage is v out v fb 1 r 1 r 2 (eq. 14) where v fb is equal to the internal reference voltage 0.6 v, r 1 is the resistance from v out to fb, which has a normal value range from 50 k to 1 m and a typical value of 220 k for applications with the typical output filter. r2 is the resistance from fb to agnd, which is used to program the output voltage according to equation 14 once the value of r 1 has been selected. an capacitor c fb needs to be employed between the v out and fb in order to provide feedforward function to achieve optimum transient response. normal value range of c fb is from 0 to 100pf, and a typical value is 15 pf for applications with the typical output filter and r1 = 220 k . table 4 provides reference values of r 1 and c fb in case of different output filter combinations. the final design may need to be fine tuned regarding to application specifications.
ncp6354 http://onsemi.com 12 table 4. reference values of feedback networks (r 1 and c fb ) for output filter conbinations (l and c) r 1 (k ) l ( h) c fb (pf) 0.47 0.68 1 2.2 3.3 4.7 c ( f) 4.7 220 220 220 220 330 330 3 5 8 15 15 22 10 220 220 220 220 330 330 8 10 15 27 27 39 22 220 220 220 220 330 330 15 22 27 39 47 56
ncp6354 http://onsemi.com 13 layout considerations electrical layout considerations good electrical layout is a key to make sure proper operation, high ef ficiency, and noise reduction. electrical layout guidelines are: ? use wide and short traces for power paths (such as pvin, vout, sw, and pgnd) to reduce parasitic inductance and high ? frequency loop area. it is also good for efficiency improvement. ? the device should be well decoupled by input capacitor and input loop area should be as small as possible to reduce parasitic inductance, input voltage spike, and noise emission. ? sw node should be a large copper pour, but compact because it is also a noise source. ? it would be good to have separated ground planes for pgnd and agnd and connect the two planes at one point. directly connect agnd pin to the exposed pad and then connect to agnd ground plane through vias. try best to avoid overlap of input ground loop and output ground loop to prevent noise impact on output regulation. ? arrange a ?quiet? path for output voltage sense and feedback network, and make it surrounded by a ground plane. thermal layout considerations good thermal layout helps high power dissipation from a small package with reduced temperature rise. thermal layout guidelines are: ? the exposed pad must be well soldered on the board. ? a four or more layers pcb board with solid ground planes is preferred for better heat dissipation. ? more free vias are welcome to be around ic and/or underneath the exposed pad to connect the inner ground layers to reduce thermal impedance. ? use large area copper especially in top layer to help thermal conduction and radiation. ? do not put the inductor to be too close to the ic, thus the heat sources are distributed. a vin gnd vout gnd cin cin ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ?????????? ??? ??? ??? ??? ??? ??? ??? ???
ncp6354 http://onsemi.com 14 ordering information device marking package shipping ? ncp6354bmtaatbg a2 wdfn8 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp6354 http://onsemi.com 15 package dimensions wdfn8 2x2, 0.5p case 511be issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ??? ??? a d e b c 0.10 pin one 2x reference 2x top view side view bottom view l d2 e2 c c 0.10 c 0.10 c 0.08 a1 seating plane 8x note 3 b 8x 0.10 c 0.05 c a b b dim min max millimeters a 0.70 0.80 a1 0.00 0.05 b 0.20 0.30 d 2.00 bsc d2 1.50 1.70 e 2.00 bsc e2 0.80 1.00 e 0.50 bsc l 0.20 0.40 1 4 8 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 pitch 1.00 2.30 1 dimensions: millimeters 0.50 8x note 4 0.30 8x detail a a3 0.20 ref a3 a detail b l1 detail a l alternate constructions ?? ?? ?? ??? 0.15 outline package e recommended k 0.25 ref 5 1.70 k on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp6354/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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